A 3.1-5GHz Low Power, High Gain and Improved Linearity Low Noise Amplifier (LNA) for Implantable Ultra Wideband Applications in CMOS Silicon-On- Sapphire (SOS) Process

Vol.1 No.4

Year: 2012

 
Issue: Sep-Nov

Title : A 3.1-5GHz Low Power, High Gain and Improved Linearity Low Noise Amplifier (LNA) for Implantable Ultra Wideband Applications in CMOS Silicon-On- Sapphire (SOS) Process 

  

Author Name : Ayobami Iji, Xie Zhu

   

Synopsis :

High data rate implantable wireless systems come with many challenges, chief among them being low power operation and high path loss. LNAs designed for this application must include high gain, low noise figure (NF) and better linearity at low power consumption within the required frequency. In this paper, our design is based on Impulse Response (IR) Ultra Wide-Band (UWB) operating at (3.1 — 5) GHz. We report the design and measurement of an LNA with 2.4dB NF, 17.3dB of gain and input intercept point of 2dBm consuming 4mW, which make it suitable for implantable radio applications. The process technology used here is 0.25µm CMOS Silicon on Sapphire (SOS) process.